This invention relates in general to a semiconductor device and a method for its fabrication, and more particularly to a BiCMOS device on a silicon-on-insulator (SOI) substrate and method of fabrication.
In BiCMOS integrated circuit technology a continuing goal is to fabricate high performance integrated circuits having improved functionally. A common approach to achieving this goal is to reduce the size and separation distance of the various circuit components and thereby increase the packing density. A requirement for electrical isolation of the various circuit components while simultaneously controlling the amount of parasitic capacitance within the circuit presents an obstacle to a simple size reduction of the circuit components. For example, heavily doped PN junctions, in addition to having a large intrinsic capacitance, can also generate a large parasitic capacitance arising from the overlap of their associated depletion regions when the junctions are brought into close proximity to each other. The high intrinsic capacitance, which and proximity induced parasitic capacitance slow the signal transmission rate and switching speed of the circuit. In the bipolar portion, the excessive collector-substrate capacitance slows the switching speed of vertical bipolar transistors commonly used in both bipolar and BiCMOS circuits. The parasitic capacitance problem is particularly acute in the CMOS device portion which has both NMOS and PMOS transistors in close proximity to one another. Typically, a well region of one conductivity type is formed in a single crystal silicon substrate of an opposite conductivity type to provide an electrically isolated region in which to construct one of the CMOS transistors. Although effective, the formation of a well region sets a minimum separation distance for the two transistors. A better solution is to simply isolate the transistors with an oxide isolation structure.
It has been recognized that improved CMOS device performance and increased packing density can be obtained by fabricating the CMOS transistors on an SOI substrate. Using such a substrate eliminates the need to form a well region; therefore, the minimum separation distance can be reduced. The performance characteristics of CMOS devices on an SOI substrate include: improved subthreshold slope, reduced short channel effects, reduced electric field strength, increased transconductance, and better immunity to soft errors. Recent advances in SIMOX (Separation by Implanted Oxygen) technology have reduced the defect density and improved the interface characteristics of SOI substrates formed using a SIMOX process making this technique attractive for SOI substrate formation. Given the improved CMOS performance obtainable with an SOI substrate and the potential for reduced bipolar collector capacitance, it would be advantageous if a BiCMOS device existed having an SOI substrate formed with a SIMOX process.